<%@ page language="java" contentType="text/html" %> <%-- Include common initialisation code --%> <%@ include file="/arch/common.jsp" %> <%-- The current tab --%> <% String currentTab = "Research"; %> <%-- Content of navigation pane --%> <%@ include file="nav.jsp" %> <% showCurrentLink=true; %> <%-- Current navigation location --%> <% String currentNav = "Reports and Theses"; %> <%-- Include the code for the document header --%> <%@ include file="/arch/header.jsp" %>

Research Report CS-RR-164

<%-- Include the code for the lines and navigation --%> <%@ include file="/arch/middle.jsp" %>

Paul Chown, D.W. Walton and Graham R. Nudd, VLSI Design of a Pipelined CORDIC Processor (October 1, 1990).

Abstract

In this report we discuss the VLSI realisation of a pipelined CORDIC arithmetic unit to perform stable matrix row operations for the solution of systems of linear equations. The algorithmic considerations of the CORDIC process are highlighted and a chip level architecture is derived from these to implement the algorithm in a pipelined manner. We then proceed to give details of the 2pm CMOS processor that has been designed to implement that architecture.

<%@ include file="hardcopy.html" %> <%-- Include the code for the document footer --%> <%@ include file="/arch/footer.jsp" %>